Senior/Staff Nanofabrication and Characterization Engineer
Neurophos · Austin, Texas, United States · onsite
USD 160,000 to 190,000 per year
ABOUT NEUROPHOS
The demand for new data centers and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck means rethinking the fundamental architecture of inference compute. The industry's current path can't meet the need, so we're taking a different approach.
Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A https://www.neurophos.com/110m-raise led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others.
Join us and shape the future of computing!
Location: Austin, TX. Full-time onsite position.
Reports To: Chief Scientist
FLSA Status: Exempt
POSITION OVERVIEW
We are seeking a hands-on Nanofabrication and Characterization Engineer to build and characterize prototype metasurface chips for our optical vector-matrix multiplication (OVMM) engine. Prototypes made in university cleanrooms let us try new metasurface designs, materials, and process changes in weeks rather than waiting on a full foundry cycle. This role owns that fast path: you will turn electromagnetic designs into masks and process flows, fabricate multilevel metal–dielectric nanostructures, integrate the active tunable layer and package the device, and measure what you built so every run teaches us something.
You will spend most of your time in shared-user university nanofabrication facilities and in our own lab: running lithography, deposition, etch, and planarization steps, inspecting and cross-sectioning devices, and measuring their optical and electro-optic response. The rest of your time goes to process documentation, run tracking, and data analysis. If you combine strong cleanroom process skills with the drive to test your own devices, this role will let you own the metasurface prototyping line, from design to measured device.
KEY RESPONSIBILITIES
- Process Flow Development: Turn metasurface designs into complete, multi-step process flows and travelers. Select lithography, deposition, etch, and planarization steps that meet target dimensions and tolerances with the tools at hand.
- Nanoscale Lithography: Pattern sub-200 nm features and align multiple layers using electron-beam lithography and optical or deep-UV steppers. Develop and maintain dose, proximity-correction, and resist recipes.
- Thin-Film Deposition and Etch: Deposit and etch metals, dielectrics, and thin conformal liners (sputtering, evaporation, PECVD, ALD, RIE/ICP). Control thickness, sidewall profile, and aspect ratio to nanometer-level tolerances.
- Multilevel Integration: Build stacked metal–dielectric structures with vias and planarization (CMP, damascene, or lift-off). Diagnose and fix yield problems that arise between layers: misalignment, dishing, voids, and adhesion.
- Active Layer and Device Assembly: Integrate the electro-optically tunable material layer, including surface preparation, alignment and encapsulation layers, cell assembly, and sealing. Dice, mount, and wire-bond devices for testing.
- Process Metrology: Inspect every run with SEM, FIB cross-sections, AFM, profilometry, and ellipsometry. Feed measured dimensions back into the design so it models the as-built device.
- Optical and Electro-Optic Characterization: Measure the reflectance, spectra, polarization response, and voltage-dependent tuning of finished devices on microscope-based optical benches. Compare results against simulation and trace gaps to specific design or process causes.
- Facility and Run Management: Hold access and training at university cleanroom facilities, schedule tool time, manage materials and consumables, and maintain a steady run cadence with clear records of what was built and why.
Secondary Responsibilities
- Design metasurface unit cells and arrays using full-wave electromagnetic simulation in partnership with the modeling team, set geometries and tolerances based on what the process can produce, and generate mask layouts.
- Maintain process recipes, travelers, run logs, and characterization reports so that any run can be repeated and audited.
- Supply the modeling and design teams with as-fabricated dimensions, material properties, and process tolerances that set design rules for future layouts.
- Flag to the Architecture & Requirements team any design feature or tolerance that measured process data shows is unachievable or high-risk.
- Help transfer processes and lessons learned to foundry partners, and compare foundry-built and prototype devices.
- Mentor engineers and technicians in cleanroom practice, process safety, and metrology.
QUALIFICATIONS
- Degree: MS or PhD in Electrical Engineering, Materials Science, Applied Physics, Optics, or a closely related field, with a thesis or work centered on nanofabrication.
- Experience: 3+ years of hands-on cleanroom experience fabricating nanophotonic, metasurface, plasmonic, MEMS, or semiconductor devices, including independent ownership of multi-step process flows.
- Nanolithography: Direct experience with electron-beam lithography and multilayer alignment at sub-200 nm feature sizes, including resist processing and dose and proximity correction.
- Deposition and Etch: Practical command of metal and dielectric deposition and dry etch, including recipe development for profile, selectivity, and uniformity.
- Metrology: Proficiency with SEM, AFM, ellipsometry, and profilometry; FIB cross-sectioning experience strongly desired.
- Optical Characterization: Experience measuring the optical response of nanostructured devices with microscope-based reflection or transmission spectroscopy and polarization optics.
- Software for Analysis: Proficiency in Python (and/or MATLAB) for process data analysis, image analysis, and automated measurement, plus layout tools such as KLayout or L-Edit for mask design.
- Safety: Strong cleanroom safety practices with hazardous chemicals and gases, and laser safety training for optical bench work.
- Communication: Clear technical documentation and strong collaboration with device designers, modeling engineers, packaging engineers, and facility staff.
PREFERRED SKILLS
- Experience in a university or shared-user nanofabrication facility, including quickly qualifying new tools and working within shared tool schedules.
- Damascene metallization, CMP, or other planarization processes for multilevel interconnect-like stacks.
- Atomic layer deposition of conformal dielectric or metal-nitride liners in high-aspect-ratio features.
- Experience with liquid crystals, electro-optic polymers, phase-change materials, or other tunable optical materials, including alignment layers and cell assembly.
- Post-CMOS processing or heterogeneous integration on foundry wafers or dies.
- Dicing, die attach, wire bonding, and electrical probing of fabricated devices.
- Nanophotonic or metasurface design experience with full-wave electromagnetic simulation (FDTD, FEM, RCWA) and simulation-to-layout workflows. This is the path to owning the full design-to-characterization cycle.
- Statistical process control, design of experiments, and yield analysis across wafers and runs.
- Experience transferring a process to a commercial foundry or working with foundry design rules.
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