Cadence: open roles and hiring stats
Cadence has 43 open roles on AYN.
Cadence shows pay on 74% of its 43 open postings.
43 roles listed in the last 30 days; 0 no longer listed.
3 updates to its postings in the last 30 days.
Where it is hiring
San Jose, United States (31); Austin, United States (5); VALBONNE Sophia, France (4); AUSTIN 03, United States (1); Burlington, Massachusetts, United States (1); Home Or, United States (1)
Work mode is stated on 3 of 43 postings.
Benefits mentioned in its postings: Retirement plan (32), Equity (32), Paid time off (32), Health insurance (32).
Open roles posted in the last 7 days
- Program Manager for Academic Network (Austin, United States)
- Principal AE (STA - SignOff) (Austin, United States)
- RTL2GDS IC Sr. Principal Design Engineer (San Jose, United States)
- Physical Design and Signoff, Sr. Principal AE (San Jose, United States)
- RTL2GDS AE Architect (San Jose, United States)
- Lead Software Engineer, Robotics Simulation (San Jose, United States)
- Lead EDA Software Engineer (C++, Characterization) (San Jose, United States)
- RTL2GDS Principal AE (San Jose, United States)
- Lead Software Engineer, ML/RL for robotics (San Jose, United States)
- Intern: AI for Smarter ATE Test Development & Debug (VALBONNE Sophia, France)
- Principal Product Engineer (Analog Design Automation) (San Jose, United States)
- IT Staff Storage Engineer (San Jose, United States)
- Lead Software Engineer (San Jose, United States)
- Software Security Architect (San Jose, United States)
- Principal Analog IC Design Engineer, High Speed SerDes (San Jose, United States)
- Principal Product Engineer (Analog Design Automation) (San Jose, United States)
- Product Engineering Architect (3D IC, Heterogeneous Integration & Advanced Packaging) (San Jose, United States)
- Infrastructure Integration Lead (M&A) (San Jose, United States)
- AI Security Architect (San Jose, United States)
- Product Engineer (Analog Circuit Design) (San Jose, United States)
- Intern: AI for Silicon Test Data Analytics & Failure Analysis (VALBONNE Sophia, France)
- Director of Software Security (San Jose, United States)
- IC design Implementation and SignOff Architect, (STA SignOff) (Home Or, United States)
- Director, Product Management — Custom & Analog Design Solutions (San Jose, United States)
- Senior Systems Engineer (HPC/Server Farm) (San Jose, United States)
- Cloud Support Engineer (San Jose, United States)
- Sr Principal HW Design Engineer-Emulation Acceleration System Platform (San Jose, United States)
- Chip Lead / Physical Design Director (AUSTIN 03, United States)
- Quantum Product Engineer (San Jose, United States)
- Event Technology Specialist (Austin, United States)
- Lead Product Engineer (San Jose, United States)
- Sr Custom Silicon Sales Executive (Burlington, Massachusetts, United States)
- SW Development and Release Operations Technical Program Manager (San Jose, United States)
- Intern Mixed Signal IP (VALBONNE Sophia, France)
- Sr. Interface IC, IP Sales Executive II (San Jose, United States)
- Principal Analog IC Design Engineer, High Speed SerDes (San Jose, United States)
- Sr Principal Engineer -SIPI (San Jose, United States)
- Lead Software Engineer (Austin, United States)
- Intern AFG Memoire (VALBONNE Sophia, France)
- Senior AE, SerDes Design IP (San Jose, United States)